Integrated circuits (ICs) include electronic components, such as transistors, diodes and resistors, that are electrically connected by metal interconnects to form electronic circuits, built on semiconductor substrates, typically wafers. Metal interconnects include horizontal metal lines, typically in several levels, vertical metal vias that connect the horizontal metal lines, and vertical metal contacts that connect components in an IC to a lowest set of horizontal metal lines. Feature sizes and separation distances in ICs are shrinking on a well known trend of technology nodes, articulated in Moore's Law. In each new technology node, it is common practice to scale minimum lateral dimensions and lateral spacing of features in ICs, including widths and spacing of horizontal metal lines, vertical metal vias and vertical metal contacts by a factor applied to all features, typically approximately 70 percent. During IC fabrication, patterns for forming horizontal metal lines, vertical metal vias and vertical metal contacts are generated by photolithographic processes. Feature sizes and spacing smaller than 100 nanometers are often close to a diffraction limit of photolithographic equipment used to generate their patterns. It is common for sizes and spacing of vertical metal vias and vertical metal contacts, when arranged in an orthogonal array of minimum pitch, to be closer to, or even less than, a diffraction limit of corresponding photolithographic equipment than for sizes and spacing of minimum width horizontal metal lines arranged in a minimum pith configuration.